Flash memories have become increasingly popular in recent years. A typical flash memory comprises a memory array having a large number of memory cells arranged in blocks. Each of the memory cells is fabricated as a field-effect transistor having a control gate and a floating gate. The floating gate is capable of holding a charge and is separated from source and drain regions contained in a substrate by a layer of thin oxide. Each of the memory cells may be electrically charged by injecting electrons from the substrate through the oxide layer onto the floating gate. The charge may be removed from the floating gate by tunneling the electrons to the source region or an erase gate during an erase operation. The data in flash memory cells are thus determined by the presence or absence of electrical charges in the floating gates.
FIG. 1 illustrates two exemplary prior art flash memory cells 2 and 20, wherein flash memory cells 2 and 20 share a common source region 16 and a common erase gate 18. Flash memory cell 2 includes a floating gate 4, a control gate 6 over and electrically insulated from floating gate 4, and a word-line node 10 over a channel 12 and on sidewalls of floating gate 4 and control gate 6. Word-line 10 controls the conduction of channel 12, which is between bit-line node 14 and source region 16. During a program operation, a voltage is applied between bit-line node 14 and source region 16, with, for example, a bit-line node voltage of about 0.4V and a source voltage of about 5V. Word-line 10 is applied with a voltage of 1.1V to turn on channel 12. Therefore, a current (hence electrons) flows between bit-line node 14 and source region 16. A high voltage, for example, about 10V, is applied on control gate 6, and thus the electrons are programmed into floating gate 4 under the influence of a high electrical field. During an erase operation, a high voltage, for example, 11V, is applied to erase gate 18. Word-line 10 is applied with a low voltage such as 0V, while source region 16, bit-line node 14 and control gate 6 are applied with a voltage of 0V. Electrons in floating gate 4 are thus driven into erase gate 18.
FIG. 2a illustrates a cross-sectional view of a structure 200 of prior art flash memory cells. Structure 200 of flash memory cells displays the presence of a spacer 205 between word-line 10 and floating gate 4. Spacer 205 may be used to prevent or reduce leakage current between word-line 10 and floating gate 4, as well as preventing induced reverse tunneling voltage failure. Therefore, spacer 205 may be created with a desired thickness that is based on manufacturing process. Furthermore, spacer 205 should have uniform thickness, which may lead to more consistent behavior. Typically, spacer 205 is formed from an oxide layer. However, spacer 205 formed solely from an oxide layer may be prone to damage from other fabrication process steps and uniformity may be difficult to achieve with an oxide layer alone.
FIGS. 2b and 2c illustrate cross-sectional views of structures of prior art flash memories. FIG. 2b illustrates a thin spot 210 formed in spacer 205 (formed from an oxide layer) that results from residue from an etch operation. Thin spot 210 in spacer 205 may lead to increased leakage current and/or induced reverse tunneling voltage failure due to non-uniformity in spacer 205. FIG. 2c illustrates a sharp point 215 in a floating gate poly layer interface with a word-line. Sharp point 215, resulting from a poly etch, may lead to increased leakage current and/or induced reverse tunneling voltage failure.
There is therefore, a need for flash memories having consistent and uniform spacers between floating gates and word-lines, as well as more consistent spacers, to reduce leakage current and to prevent induced reverse tunneling voltage failure. This need may continue to increase in importance as fabrication process feature sizes continue to decrease.